In the field of semiconductor processor chip fabrication, single-chip processors were fabricated by many companies during the early stages of processor technology. In the last decade or so, as Moore's Law has continued to shrink dimensions, many companies and other entities have designed processor chips with multiple processors on a single layer. However, as the number of processors per chip continues to increase, on chip communication between processors becomes problematic. For example, as the 2-D size of the processor chip increases to accommodate more processors, the length of the horizontal wiring between the processors increases (in the range of mm or cm) resulting in cycle delays in the communication between processors, and requiring the use of high-powered on-chip drivers along communication paths between processors. Furthermore, the cycle delay with respect to communication between processors increases as the operating frequency increases. Furthermore, as integration density increases, it becomes increasingly expensive in terms of chip area and problematic in terms of wire routing and congestion to include test infrastructure (e.g., scan chains, scan chain control circuitry, BIST (Built-in-Self-Test) modules, etc.), calibration circuitry, and performance instrumentation as part of the functional system circuitry of a given chip.